There is a need for multiple clocks in today's digital circuitry, especially in power management integrated circuits. It is often necessary to switch the source of a clock line while the circuit is running. This may be implemented by multiplexing different frequency clock sources in the hardware, controlling the multiplexer select line by the internal logic. The clock frequencies may be totally unrelated to each other or they may be multiples of each other.
U.S. Pat. No. 7,225,419 (Behnen, et al.) describes a method that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.
U.S. Pat. No. 5,319,254 (Goetting) shows a latch that may be formed as a two-part structure, one part for data input and one part for feeding back the data to form the latch. A clock signal controls whether data from a data input terminal would be forwarded to the output or whether the output signal will be provided as input and forwarded, thus forming the latch. A problem called the static ones hazard, namely registering a logical 0 when data input is logical 1, can occur with a latch of this logic structure when the circuit is entering the latch mode. In accordance with the invention, this static ones hazard is avoided by controlling trip points in the gates of the cell and input buffers of the cell so that the cell implements a make-before-break transition.
U.S. Pat. No. 7,010,713 (Roth, et al.) describes a synchronization circuit for re-synchronizing data from an input clock to an output clock. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock, which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
FIG. 1 shows two typical capacitive converters, a ½ down converter 110 and a 2× up-converter 120, in charge-pump configurations of the related art. The charge-pumps comprise input signal VIN, output signal VOUT, capacitors CF and CR, and switches F1 and F2.
FIG. 2 illustrates a signal diagram for equal, and non-overlapping, phases of a charge-pump. The charge pump has two sets of switches, with signals that control their switching, and are denoted by phase F1 and F2. During phase F1, flying capacitor CF is discharged through the F1 switches, and during phase F2, through the F2 switches. These principles can be extended to N phase charge-pumps, the N phases being either equal (2π/1, . . . 2π/N} or having different durations to optimize the CF discharge.
FIG. 3 shows a charge-pump integrated in a Power Management Integrated Circuit (PMIC) system 300 with other capacitive/inductive converters. The channels 303, 304, and 305 are regulated power sources like buck converters or charge-pumps, taking their source from, for example a battery. The PMIC system comprises system oscillator 301 and digital control 302. Very often the application wants all the switching frequencies of the clock channels CLK1, CLK2, and CLK3 to be equal, for example 2 MHz, and placed in a well controlled channel for Electro Magnetic Interference (EMI) reasons. Further, the application also wants to control the phase of each channel. For example, one channel may be very noisy and may pollute the power rails common to other channels, triggering false detections. If the phases are separated with respect of the known operating points of each channel, then one channel can switch while the other ones do not, and remain unaffected. In addition, if there is any phase discontinuity in the switching, the flying capacitor CF in the FIG. 1 would not have the time to deliver its charge to the output, and VOUT would glitch.